This section contains a brief description of the LEON3 SPARC V8 processor implementation developed by Gaisler Research, with an emphasis on information. LEON3 is a synthesizable VHDL model of a bit processor compliant with the SPARC V8 architecture. The processor is highly configurable, and particularly. LEON3 Processor. SPARC V8 instruction set with V8e extensions; Advanced 7- stage pipeline; Hardware multiply, divide and MAC units; High-performance, fully .

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Debugging is generally done using the gdb debugger, and a graphical front-end such as DDD or Eclipse.

Retrieved from ” https: This page presents the major microprocessors used or to be used in most European space applications. While the LEON2 -FT design can be extended and re-used in other designs, its structure does not emphasise re-using parts of the design as building blocks or enable designers to easily incorporate new IP pfocessor in the design. To maintain correct operation in the presence of SEUs, extensive error procesdor and error handling functions were needed.

LEON3 Processor | eASIC Corporation

For other uses, see Leon disambiguation. Lleon3 certification was completed on May 1, SnapGear Linux is a full source package, containing kernel, libraries and application code for rapid development of embedded Linux systems. Views Read Edit View history. Branch prediction, 1-cycle load latency and a 32×32 multiplier results in a performance of 1.


Up to 16 CPU can be used in procexsor multiprocessing configuration. LEON3 is also available under a low-cost commercial license, allowing it to be used in any commercial application to a fraction of the cost of comparable IP cores.

LEON3 32-bit processor core

Please improve this by adding secondary or tertiary sources. It has been designed for operation in the harsh space environment, and includes functionality to detect and correct procrssor event upset SEU errors in all on-chip RAM memories.

It is thus possible to instantiate several processor cores in the same design with different configurations.

The NGMP has the following on-chip functions: Airbus Defense and Space. A single cross-compilation tool-chain is provided which is capable of compiling the kernel and applications for any configuration. The full source code is available under the GNU GPL license, allowing free and unlimited use for research and education.

Archived copy as title Webarchive template wayback links Articles lacking reliable references from November All articles lacking reliable references Articles containing Spanish-language text Articles with Curlie links. Flip-flops are protected by triple modular redundancy and all internal and external memories are protected by EDAC or parity leoj3.

More information regarding these models can is available on the Aeroflex Gaisler website. This article is about the family of microprocessors.

It is possible to perform source-level symbolic debugging, either on a simulator or using real target hardware. By using this pricessor, you agree to the Terms of Use and Privacy Policy. The configuration tool not only configures the processor, but also other on-chip peripherals such as memory controllers and network interfaces.


You have already rated this page, you can only rate it once! From Wikipedia, the free encyclopedia. For industrial and high-rel applications, ports for VxWorks 5.

LEON3 Processor – MechatronicsUSP

It is highly configurable, and was designed for embedded applications with pprocessor following features on-chip: The fault-tolerance is provided at design VHDL level, and does not require an SEU-hard semiconductor process, nor a custom cell library or special back-end tools. This section and the subsequent subsections focus on the LEON processors as soft IP cores and summarise the main features of each processor version and the infrastructure with which the processor is packaged, referred to as a LEON distribution.

This page was last edited on 23 Decemberat Retrieved from ” http: Archived from the original PDF on Another objective was to be able to manufacture in a Single event upset SEU tolerant sensitive semiconductor process.